SK Hynix to Build $106 Billion Fab Cluster: 800,000 Wafer Starts a Month

Capping off a busy week for fab-related news, South Korea authorities this week gave SK Hynix a green light to build a new, 120 trillion won ($106.35 billion) fab complex. The fab cluster will be primarily used to build DRAM for PCs, mobile devices, and servers, using process technologies that rely on extreme ultraviolet lithography (EUV). The first fab in the complex will go online in 2025.

The new cluster will house four huge semiconductor fabrication plants, which will be located on a 4.15 million square-meter site, reports The Korea Herald. The four fabs will have a planned capacity of around 800,000 wafer starts per month (WSPM), which will make the site one of the world’s biggest semiconductor production hubs. Keeping in mind that we are dealing with EUV fabs, it is not surprising that a huge 200,000-WSPM plant with EUV tools will cost SK Hynix north of $25 billion. The fab cluster will be located near Yongin, South Korea, 50 kilometers south of Seoul, according to Yonhap news agency that cites the Ministry of Trade, Industry and Energy.

The new fabs will be used to make various types of DRAM using SK Hynix’s upcoming production technologies that will use extreme ultraviolet (EUV) lithography. And with a start date still years away, we’re likely looking at a fab that will be used to manufacture DDR5, LPDDR5X, and other future types of DRAM.

SK Hynix reportedly plans to start construction of the first fab in the Yongin cluster in the fourth quarter of 2021. Given the expected size of the massive building and the amount of time needed to folly load it with production equipment, SK Hynix expects this first fab to be completed in 2025.

It is necessary to note that just several years ago SK Hynix and Samsung used to build fabs that could produce both DRAM and NAND flash memory – or at least be converted with a minimal amount of effort. This is not the case today as DRAM production now heavily relies on lithography equipment, whereas 3D NAND production uses loads of etching tools, which is why the fabs for different types of memory have to be equipped completely differently.

The fab cluster in Yongin will be SK Hynix’s second major DRAM site in South Korea after the company’s primary DRAM hub near Icheon that houses its M10, M14, and M16 fabs. The M16 fab was completed in February and will be used for DRAM production using SK Hynix’s EUV-based 1a process technology starting the second half of 2021.

Capping off a busy week for fab-related news, South Korea authorities this week gave SK Hynix a green light to build a new, 120 trillion won ($106.35 billion) fab complex. The fab cluster will be primarily used to build DRAM for PCs, mobile devices, and servers, using process technologies that rely on extreme ultraviolet lithography (EUV). The first fab in the complex will go online in 2025.

The new cluster will house four huge semiconductor fabrication plants, which will be located on a 4.15 million square-meter site, reports The Korea Herald. The four fabs will have a planned capacity of around 800,000 wafer starts per month (WSPM), which will make the site one of the world's biggest semiconductor production hubs. Keeping in mind that we are dealing with EUV fabs, it is not surprising that a huge 200,000-WSPM plant with EUV tools will cost SK Hynix north of $25 billion. The fab cluster will be located near Yongin, South Korea, 50 kilometers south of Seoul, according to Yonhap news agency that cites the Ministry of Trade, Industry and Energy.

The new fabs will be used to make various types of DRAM using SK Hynix's upcoming production technologies that will use extreme ultraviolet (EUV) lithography. And with a start date still years away, we're likely looking at a fab that will be used to manufacture DDR5, LPDDR5X, and other future types of DRAM.

SK Hynix reportedly plans to start construction of the first fab in the Yongin cluster in the fourth quarter of 2021. Given the expected size of the massive building and the amount of time needed to folly load it with production equipment, SK Hynix expects this first fab to be completed in 2025.

It is necessary to note that just several years ago SK Hynix and Samsung used to build fabs that could produce both DRAM and NAND flash memory – or at least be converted with a minimal amount of effort. This is not the case today as DRAM production now heavily relies on lithography equipment, whereas 3D NAND production uses loads of etching tools, which is why the fabs for different types of memory have to be equipped completely differently.

The fab cluster in Yongin will be SK Hynix's second major DRAM site in South Korea after the company's primary DRAM hub near Icheon that houses its M10, M14, and M16 fabs. The M16 fab was completed in February and will be used for DRAM production using SK Hynix's EUV-based 1a process technology starting the second half of 2021.

TSMC to Spend $100B on Fabs and R&D Over Next Three Years: 2nm, Arizona Fab & More

TSMC this week has announced plans to spend $100 billion on new production facilities as well as R&D over the next three years. The world’s largest contract maker of chips says that its fabs are currently working at full load, so to meet demand for its services going forward it will need (much) more capacity. Among TSMC’s facilities to go online in the next three to four years are the company’s fab in Arizona as well as its first 2nm-capable fab in Taiwan.

“TSMC is entering a period of higher growth as the multiyear megatrends of 5G and HPC are expected to fuel strong demand for our semiconductor technologies in the next several years,” a statement by TSMC with the Taiwan Stock Exchange reads. “In addition, the COVID-19 pandemic also accelerates digitalization in every aspect. In order to keep up with demand, TSMC expects to invest $100 billion over the next three years to increase capacity to support the manufacturing and R&D of advanced semiconductor technologies. TSMC is working closely with our customers to address their needs in a sustainable manner.”

$100 Billion to Be Spent on Fabs

TSMC’s capital expenditures (CapEx) budget last year was $17.2 billion, whereas its R&D budget was $3.72 billion, or approximately 8.2% of its revenue. This year the company intends to increase its CapEx to somewhere in the range of $25 to $28 billion, which would make for a 45% to 62% year-over-year increase in that spending. The company’s R&D spending will also rise as its revenue is expected to grow. In total, TSMC plans to invest around $30 billion or more on CapEx and R&D this year. Taken altogether, if the company intends to spend around $100 billion from 2021 through 2023, its expenditures in the next two years will be roughly flat with 2021, something that should please its investors.

TSMC has a number of important fab projects ahead of it.

  • First up, the company needs to build and equip its N5-capable fab in Arizona. The facility will cost around $12 billion, will have a capacity of 20,000 wafer starts per month (WSPM), and will come online in 2024. A recent rumor indicates that TSMC might actually increase capacity of the facility and/or equip it for a more advanced fabrication process, which will increase its cost, but TSMC has never confirmed this information.
  • Secondly, TSMC will need to equip its N3-capable fab in Tainan, Taiwan, which is projected to start volume production in the second half of 2022.
  • TSMC’s third capital-expensive project is the company’s N2 (2nm) qualified GigaFab in Hsinchu, Taiwan. Furthermore, TSMC is mulling to build another N2-capable fab in Baoshan, Taiwan. Meanwhile, TSMC still has to complete development of its GAAFET-based N2 node.
  • Last but not least, TSMC is set to build two more advanced packaging facilities in Taiwan. The company already has four of such facilities, but it believes that demand for chip stacking and advanced packaging will rise in the future and it will need more capacities. Chip packaging factories are not as expensive as semiconductor production facilities, but they still cost quite a lot.

Recently TSMC wrote a letter to its customers where it explained that its fabs have been fully utilized for about a year now and it still cannot meet rising demand for chips. To that end, the company would have to ‘suspend wafer price reductions for a year from the start of 2022,’ according to a Bloomberg report.

Competition Intensifying

Right now, TSMC is the world’s largest contract maker of chips with no rivals that can match its total production capacity. A some of TSMC’s rivals, including GlobalFoundries and UMC, have pulled the plug on development of their leading-edge fabrication processes, so the number of companies that can offer leading-edge nodes has decreased. Yet paradoxically, the competition is also escalating in other respects.

Samsung Semiconductor, which has foundry, DRAM, storage, SoC, and a number of other operations, has been increasing its CapEx investments in the recent years. The company spent $93.2 billion on chip production from 2017 to 2020 and is on track spend another ~$28 billion in 2021, according to IC Insights. Samsung Foundry is still several times smaller than TSMC in terms of sales and capacity, but the gap is closing.

In addition to Samsung Foundry, Intel recently introduced its integrated device manufacturer 2.0 (IDM 2.0) plan that includes offering advanced foundry services and essentially compete against TSMC (while also using its services when needed). Intel has already announced plans to invest $20 billion in two new fabs in Arizona and said it would invest more in expansion of chip production in other parts of the USA as well as in Europe and other parts of the world.

To stay ahead of existing and emerging rivals, TSMC needs to keep investing in R&D and expand its production capacities, so a $100 billion investment plan will be instrumental for these purposes.

TSMC this week has announced plans to spend $100 billion on new production facilities as well as R&D over the next three years. The world's largest contract maker of chips says that its fabs are currently working at full load, so to meet demand for its services going forward it will need (much) more capacity. Among TSMC's facilities to go online in the next three to four years are the company's fab in Arizona as well as its first 2nm-capable fab in Taiwan.

"TSMC is entering a period of higher growth as the multiyear megatrends of 5G and HPC are expected to fuel strong demand for our semiconductor technologies in the next several years," a statement by TSMC with the Taiwan Stock Exchange reads. "In addition, the COVID-19 pandemic also accelerates digitalization in every aspect. In order to keep up with demand, TSMC expects to invest $100 billion over the next three years to increase capacity to support the manufacturing and R&D of advanced semiconductor technologies. TSMC is working closely with our customers to address their needs in a sustainable manner."

$100 Billion to Be Spent on Fabs

TSMC's capital expenditures (CapEx) budget last year was $17.2 billion, whereas its R&D budget was $3.72 billion, or approximately 8.2% of its revenue. This year the company intends to increase its CapEx to somewhere in the range of $25 to $28 billion, which would make for a 45% to 62% year-over-year increase in that spending. The company's R&D spending will also rise as its revenue is expected to grow. In total, TSMC plans to invest around $30 billion or more on CapEx and R&D this year. Taken altogether, if the company intends to spend around $100 billion from 2021 through 2023, its expenditures in the next two years will be roughly flat with 2021, something that should please its investors.

TSMC has a number of important fab projects ahead of it.

  • First up, the company needs to build and equip its N5-capable fab in Arizona. The facility will cost around $12 billion, will have a capacity of 20,000 wafer starts per month (WSPM), and will come online in 2024. A recent rumor indicates that TSMC might actually increase capacity of the facility and/or equip it for a more advanced fabrication process, which will increase its cost, but TSMC has never confirmed this information.
  • Secondly, TSMC will need to equip its N3-capable fab in Tainan, Taiwan, which is projected to start volume production in the second half of 2022.
  • TSMC's third capital-expensive project is the company's N2 (2nm) qualified GigaFab in Hsinchu, Taiwan. Furthermore, TSMC is mulling to build another N2-capable fab in Baoshan, Taiwan. Meanwhile, TSMC still has to complete development of its GAAFET-based N2 node.
  • Last but not least, TSMC is set to build two more advanced packaging facilities in Taiwan. The company already has four of such facilities, but it believes that demand for chip stacking and advanced packaging will rise in the future and it will need more capacities. Chip packaging factories are not as expensive as semiconductor production facilities, but they still cost quite a lot.

Recently TSMC wrote a letter to its customers where it explained that its fabs have been fully utilized for about a year now and it still cannot meet rising demand for chips. To that end, the company would have to 'suspend wafer price reductions for a year from the start of 2022,' according to a Bloomberg report.

Competition Intensifying

Right now, TSMC is the world's largest contract maker of chips with no rivals that can match its total production capacity. A some of TSMC's rivals, including GlobalFoundries and UMC, have pulled the plug on development of their leading-edge fabrication processes, so the number of companies that can offer leading-edge nodes has decreased. Yet paradoxically, the competition is also escalating in other respects.

Samsung Semiconductor, which has foundry, DRAM, storage, SoC, and a number of other operations, has been increasing its CapEx investments in the recent years. The company spent $93.2 billion on chip production from 2017 to 2020 and is on track spend another ~$28 billion in 2021, according to IC Insights. Samsung Foundry is still several times smaller than TSMC in terms of sales and capacity, but the gap is closing.

In addition to Samsung Foundry, Intel recently introduced its integrated device manufacturer 2.0 (IDM 2.0) plan that includes offering advanced foundry services and essentially compete against TSMC (while also using its services when needed). Intel has already announced plans to invest $20 billion in two new fabs in Arizona and said it would invest more in expansion of chip production in other parts of the USA as well as in Europe and other parts of the world.

To stay ahead of existing and emerging rivals, TSMC needs to keep investing in R&D and expand its production capacities, so a $100 billion investment plan will be instrumental for these purposes.

EUV Pellicles Ready For Fabs, Expected to Boost Chip Yields and Sizes

Foundries started limited usage of extreme ultraviolet (EUV) lithography for high-volume manufacturing (HVM) of chips in 2019. At the time, ASML’s Twinscan NXE scanners were good enough for production, but the full EUV ecosystem was not quite there. One of the things that impacted EUV was the lack of protective pellicles for photomasks, which limited usage of EUV tools and affected yields. Fortunately, the situation with pellicles has finally improved thanks to the recent introduction of production-ready EUV pellicles, and matters promise to get even better in the coming years.

Protecting Precious Reticles

ASML has made a great progress with its Twinscan NXE EUV lithography tools in the recent years, improving performance of light source, availability time, and productivity. Its industry peers have also done a lot to make high-volume manufacturing (HVM) using EUV equipment possible. Still, the EUV ecosystem needs to develop further. One of the most notorious challenges the semiconductor supply chain faced with EUV is development of pellicles that were not available two years ago, which is why TSMC and Samsung Foundry had to invent ways how to use their EUV scanners without protective films.


For Reference: A 16nm TSMC Pellicle With Reticle

Pellicles protect 6×6-inch photomasks (reticles) during the chip production flow by sealing them away from particles that could land on their surface, which would otherwise damage them or introduce defects to wafers in production. Each reticle for an EUV tool costs $300,000, so chipmakers are eager to protect them against damage by particles or even the EUV radiation itself as this lowers their costs. Meanwhile, reducing risks associated with yields is perhaps even more important.

The need for pellicles, in turn, varies depending on the manufacturer and the types of photomasks employed. Intel, which is known for its big CPU dies, tends to use single-die reticles, which means that just one mask defect introduced by a particle automatically kills the whole die. Meanwhile, if a 25-die photomask is used, a particle adder will ‘only’ result in 4% lower yield (one dead die), which is why it’s been possible to get away without pellicles for smaller chips and multi-die photomasks.

ASML Leading the Pack. For Now

The industry started to develop protective films for EUV tools relatively late after it transpired that nobody can guarantee that an ultra-complex EUV scanner is 100% free of harmful particles, which is why they were not ready in 2019.

Pellicles for photomasks to be used with deep ultraviolet (DUV) lithography equipment are common and cheap. By contrast, since photomasks for EUV are different from photomasks for DUV (EUV masks are essentially 250 to 350-nm thick stacks featuring 40 to 50 alternating layers of silicon and molybdenum on a substrate), pellicles for such reticles are also quite different. In particular, the very short wavelength of EUV means that pellicles for it have a number of requirements that make them uneasy to produce and expensive. EUV pellicles have to be extremely thin, should not affect reflection characteristics of reticles, should feature a high transmission rate (the higher the rate, the higher is productivity of a scanner), should sustain high EUV power levels, and withstand extreme temperatures (from 600ºC to 1,000ºC in the future).


ASML’s EUV Pellicle (Image Credit: Semiconductor Engineering)

“Most materials absorb very strongly at the more energetic 13.5nm EUV wavelength and, even when the most EUV-transparent materials are selected, the membranes must be extremely thin to approach 90% transmittance,” said Emily Gallagher, a principal member of technical staff at Imec. “Such thin membranes are not usually capable of maintaining sufficient strength to be free-standing at the required dimensions. Additionally, the EUV scanner environment is not compatible with many materials and will subject the pellicle to pump-vent cycles.”

To date, a number of EUV pellicle options have emerged, according to SemiEngineering:

  • ASML introduced its first EUV pellicles in 2019 and licensed the technology to Mitsui Chemicals, which intends to start their volume sales in Q2 2021. Since then, ASML has improved its pellicles.
  • Imec has disclosed test results of its pellicles based on carbon nanotubes.
  • Graphene Square, Freudenberg Sealing Technologies (FST), and some universities are developing their own pellicles.

So far, only ASML has managed to create commercially viable pellicles for EUV tools that are actually available. ASML’s pellicles are based on polysilicon that is 50 nm thick. Back in 2016, they demonstrated a 78% transmissions rate on a simulated 175W source. Currently ASML can sell a pellicle with an 88% transmission rate. And shortly, Mitsui will start supplying such pellicles in volume.

ASML’s latest prototypes made of metal silicide demonstrate a 90.6% transmission rate with 0.2% non-uniformities and less than 0.005% reflectivity on a 400W source.

“This upgrade supports our roadmap, which eventually will take source power up to 400 Watts,” said Raymond Maas, ASML’s product manager for pellicles, in an interview with Bits&Chips.nl. “The pellicle heats up to 600ºC at that power level, which the polysilicon couldn’t withstand.”

By contrast, Imec’s prototype pellicles have a transmission rate of 97.7%. In fact, in the long term, when more advanced light sources are available, more sophisticated pellicles will be needed and this is where Imec’s carbon nanotubes-based pellicles will come into play.

“Few materials have the potential of high EUV transmission beyond 90% and even fewer materials are at the same time compatible with EUV powers beyond 600W. In addition, the pellicle needs to be strong to be suspended over a large area of the mask (~110mm x 140mm),” said Joost Bekaert, a researcher from Imec.

Unfortunately, it is unclear when Imec’s carbon nanotube-based pellicles will be ready for primetime.

Summary

TSMC and Samsung Foundry have invented ways to use EUV lithography tools without pellicles on multi-die photomasks for smaller chips, but such methods are risky as any particle adder can become a yield killing defect. Furthermore, such methods are risky for bigger chips and single-die photomasks, so pellicles are critical for enabling large dies to be made with EUV tools. That said, regardless of the photomask size, pellicles are needed to improve EUV yields and reduce risks across the board.

Overall then, the use of and improvements in EUV pellicles will be a gradual process. The initial pellicles developed and made by ASML and soon to be made by Mitsui are good enough for some of today’s needs, but there is room for improvement with their transmission levels, as evidenced by the next-generation prototypes developed by ASML and Imec. Better pellicles will be needed to account for future scanners as well, since those machines will have more powerful sources. Nonetheless, since such pellicles have a number of indisputable advantages, they are going to be used by chipmakers as they can help to improve yields even at the cost of some productivity.

Foundries started limited usage of extreme ultraviolet (EUV) lithography for high-volume manufacturing (HVM) of chips in 2019. At the time, ASML's Twinscan NXE scanners were good enough for production, but the full EUV ecosystem was not quite there. One of the things that impacted EUV was the lack of protective pellicles for photomasks, which limited usage of EUV tools and affected yields. Fortunately, the situation with pellicles has finally improved thanks to the recent introduction of production-ready EUV pellicles, and matters promise to get even better in the coming years.

Protecting Precious Reticles

ASML has made a great progress with its Twinscan NXE EUV lithography tools in the recent years, improving performance of light source, availability time, and productivity. Its industry peers have also done a lot to make high-volume manufacturing (HVM) using EUV equipment possible. Still, the EUV ecosystem needs to develop further. One of the most notorious challenges the semiconductor supply chain faced with EUV is development of pellicles that were not available two years ago, which is why TSMC and Samsung Foundry had to invent ways how to use their EUV scanners without protective films.


For Reference: A 16nm TSMC Pellicle With Reticle

Pellicles protect 6×6-inch photomasks (reticles) during the chip production flow by sealing them away from particles that could land on their surface, which would otherwise damage them or introduce defects to wafers in production. Each reticle for an EUV tool costs $300,000, so chipmakers are eager to protect them against damage by particles or even the EUV radiation itself as this lowers their costs. Meanwhile, reducing risks associated with yields is perhaps even more important.

The need for pellicles, in turn, varies depending on the manufacturer and the types of photomasks employed. Intel, which is known for its big CPU dies, tends to use single-die reticles, which means that just one mask defect introduced by a particle automatically kills the whole die. Meanwhile, if a 25-die photomask is used, a particle adder will 'only' result in 4% lower yield (one dead die), which is why it's been possible to get away without pellicles for smaller chips and multi-die photomasks.

ASML Leading the Pack. For Now

The industry started to develop protective films for EUV tools relatively late after it transpired that nobody can guarantee that an ultra-complex EUV scanner is 100% free of harmful particles, which is why they were not ready in 2019.

Pellicles for photomasks to be used with deep ultraviolet (DUV) lithography equipment are common and cheap. By contrast, since photomasks for EUV are different from photomasks for DUV (EUV masks are essentially 250 to 350-nm thick stacks featuring 40 to 50 alternating layers of silicon and molybdenum on a substrate), pellicles for such reticles are also quite different. In particular, the very short wavelength of EUV means that pellicles for it have a number of requirements that make them uneasy to produce and expensive. EUV pellicles have to be extremely thin, should not affect reflection characteristics of reticles, should feature a high transmission rate (the higher the rate, the higher is productivity of a scanner), should sustain high EUV power levels, and withstand extreme temperatures (from 600ºC to 1,000ºC in the future).


ASML's EUV Pellicle (Image Credit: Semiconductor Engineering)

"Most materials absorb very strongly at the more energetic 13.5nm EUV wavelength and, even when the most EUV-transparent materials are selected, the membranes must be extremely thin to approach 90% transmittance," said Emily Gallagher, a principal member of technical staff at Imec. "Such thin membranes are not usually capable of maintaining sufficient strength to be free-standing at the required dimensions. Additionally, the EUV scanner environment is not compatible with many materials and will subject the pellicle to pump-vent cycles."

To date, a number of EUV pellicle options have emerged, according to SemiEngineering:

  • ASML introduced its first EUV pellicles in 2019 and licensed the technology to Mitsui Chemicals, which intends to start their volume sales in Q2 2021. Since then, ASML has improved its pellicles.
  • Imec has disclosed test results of its pellicles based on carbon nanotubes.
  • Graphene Square, Freudenberg Sealing Technologies (FST), and some universities are developing their own pellicles.

So far, only ASML has managed to create commercially viable pellicles for EUV tools that are actually available. ASML's pellicles are based on polysilicon that is 50 nm thick. Back in 2016, they demonstrated a 78% transmissions rate on a simulated 175W source. Currently ASML can sell a pellicle with an 88% transmission rate. And shortly, Mitsui will start supplying such pellicles in volume.

ASML's latest prototypes made of metal silicide demonstrate a 90.6% transmission rate with 0.2% non-uniformities and less than 0.005% reflectivity on a 400W source.

"This upgrade supports our roadmap, which eventually will take source power up to 400 Watts," said Raymond Maas, ASML’s product manager for pellicles, in an interview with Bits&Chips.nl. "The pellicle heats up to 600ºC at that power level, which the polysilicon couldn’t withstand."

By contrast, Imec's prototype pellicles have a transmission rate of 97.7%. In fact, in the long term, when more advanced light sources are available, more sophisticated pellicles will be needed and this is where Imec's carbon nanotubes-based pellicles will come into play.

"Few materials have the potential of high EUV transmission beyond 90% and even fewer materials are at the same time compatible with EUV powers beyond 600W. In addition, the pellicle needs to be strong to be suspended over a large area of the mask (~110mm x 140mm)," said Joost Bekaert, a researcher from Imec.

Unfortunately, it is unclear when Imec's carbon nanotube-based pellicles will be ready for primetime.

Summary

TSMC and Samsung Foundry have invented ways to use EUV lithography tools without pellicles on multi-die photomasks for smaller chips, but such methods are risky as any particle adder can become a yield killing defect. Furthermore, such methods are risky for bigger chips and single-die photomasks, so pellicles are critical for enabling large dies to be made with EUV tools. That said, regardless of the photomask size, pellicles are needed to improve EUV yields and reduce risks across the board.

Overall then, the use of and improvements in EUV pellicles will be a gradual process. The initial pellicles developed and made by ASML and soon to be made by Mitsui are good enough for some of today's needs, but there is room for improvement with their transmission levels, as evidenced by the next-generation prototypes developed by ASML and Imec. Better pellicles will be needed to account for future scanners as well, since those machines will have more powerful sources. Nonetheless, since such pellicles have a number of indisputable advantages, they are going to be used by chipmakers as they can help to improve yields even at the cost of some productivity.

SMIC to Build a New 28nm Fab in Shenzhen: Production to Start in 2022

As further evidence that the ongoing chip crunch is hitting every level of the chip manufacturing chain, Chinese chipmaker SMIC has announced plans to build a new 28nm manufacturing plant in Shenzhen, with expected start of production in 2022.

As further evidence that the ongoing chip crunch is hitting every level of the chip manufacturing chain, Chinese chipmaker SMIC has announced plans to build a new 28nm manufacturing plant in Shenzhen, with expected start of production in 2022.

AI Meets Chipmaking: Applied Materials Incorporates AI In Wafer Inspection Process

Advanced system-on-chip designs are extremely complex in terms of transistor count and are hard to build using the latest fabrication processes. In a bid to make production of next-generation chips economically feasible, chip fabs need to ensure high yields early in their lifecycle by quickly finding and correcting defects.

But finding and fixing defects is not easy today, as traditional optical inspection tools don’t offer sufficiently detailed image resolution, while high-resolution e-beam and multibeam inspection tools are relatively slow. Looking to bridge the gap on inspection costs and time, Applied Materials has been developing a technology called ExtractAI technology, which uses a combination of the company’s latest Enlight optical inspection tool, SEMVision G7 e-beam review system, and deep learning (AI) to qucikly find flaws. And surprisingly, this solution has been in use for about a year now.

Advanced system-on-chip designs are extremely complex in terms of transistor count and are hard to build using the latest fabrication processes. In a bid to make production of next-generation chips economically feasible, chip fabs need to ensure high yields early in their lifecycle by quickly finding and correcting defects.

But finding and fixing defects is not easy today, as traditional optical inspection tools don't offer sufficiently detailed image resolution, while high-resolution e-beam and multibeam inspection tools are relatively slow. Looking to bridge the gap on inspection costs and time, Applied Materials has been developing a technology called ExtractAI technology, which uses a combination of the company's latest Enlight optical inspection tool, SEMVision G7 e-beam review system, and deep learning (AI) to qucikly find flaws. And surprisingly, this solution has been in use for about a year now.

GlobalFoundries to Invest $1.4B in Expansion, Potential Earlier IPO

GlobalFoundries this week reiterated plans to invest $1.4 billion this year in expansion of its manufacturing capacities across the world. Around one third of the sum will be co-invested by GlobalFoundries’ customers who want to ensure that they have capacity allocation for years to come. The world’s fourth largest foundry is also mulling to bring forward its IPO to late 2021 ahead of its original 2022 date.

In any typical year, GlobalFoundries spends about $700 million on expansion of its production capacities, however growing demand for chips has made clear the need for faster than normal groth – as a result the company is to invest $1.4 billion on expansion this year. The money will be divided equally between GlobalFoundries’ sites in Dresden, Malta (New York) and Singapore, according to Reuters. Production capacity is expected to increase by 13% this year and by 20% next year as a result of the increased funding.

Last year GlobalFoundries said that it planned to significantly increase capacity it its Fab 1 located near Dresden. The company’s German facility produces chips using 22FDX, 28SLP, 40/45/55NV as well as BCDLite technologies that are particularly important for automotive, mobile, IoT, and industrial applications. Capacity of Fab 1 in 2021 is expected to be in the range between 400,000 and 500,000 wafer starts per year. Increasing that number means that GlobalFoundries will be able to better address high-growth applications.

GlobalFoundries expects to raise around a third of $1.4 billion from its customers that will pre-pay to guarantee supply over the following years, the CEO of the company told Reuters. He did not name the clients.

In addition to boosting its existing production facilities, GlobalFoundries is also looking forward building another fab adjacent to its Fab 8 located in Malta, New York. Funding of the new facility will largely depend on subsidies and incentives provided by the U.S. Government and the state of New York as parts of the CHIPS for America act introduced last year. It should also be noted that Fab 8 in Malta recently recieved ITAR certification for DoD production on its 45 nm process, expanding GlobalFoundries’ value as a home-grown chip manufacturer to the US government.

Back in 2020 GlobalFoundries earned approximately $5.7 billion in revenue, down from $6.176 billion in 2017. The company projects that in 2021 its revenue will grow by 9% to 10% year-over-year as a result of unprecedented demand. 

Since demand for chips is growing and governments have investments almost ready to go, it would seems to be a good time for GlobalFoundries’ initial public offering. Previously GlobalFoundries planned to go public in late 2022 or early 2023, but the company appears to be thinking about bringing it forward into the late 2021 timeframe. Currently GlobalFoundries is wholly owned by Mubadala, an Emerati state-owned holding company.

Related Reading

GlobalFoundries this week reiterated plans to invest $1.4 billion this year in expansion of its manufacturing capacities across the world. Around one third of the sum will be co-invested by GlobalFoundries' customers who want to ensure that they have capacity allocation for years to come. The world's fourth largest foundry is also mulling to bring forward its IPO to late 2021 ahead of its original 2022 date.

In any typical year, GlobalFoundries spends about $700 million on expansion of its production capacities, however growing demand for chips has made clear the need for faster than normal groth - as a result the company is to invest $1.4 billion on expansion this year. The money will be divided equally between GlobalFoundries' sites in Dresden, Malta (New York) and Singapore, according to Reuters. Production capacity is expected to increase by 13% this year and by 20% next year as a result of the increased funding.

Last year GlobalFoundries said that it planned to significantly increase capacity it its Fab 1 located near Dresden. The company's German facility produces chips using 22FDX, 28SLP, 40/45/55NV as well as BCDLite technologies that are particularly important for automotive, mobile, IoT, and industrial applications. Capacity of Fab 1 in 2021 is expected to be in the range between 400,000 and 500,000 wafer starts per year. Increasing that number means that GlobalFoundries will be able to better address high-growth applications.

GlobalFoundries expects to raise around a third of $1.4 billion from its customers that will pre-pay to guarantee supply over the following years, the CEO of the company told Reuters. He did not name the clients.

In addition to boosting its existing production facilities, GlobalFoundries is also looking forward building another fab adjacent to its Fab 8 located in Malta, New York. Funding of the new facility will largely depend on subsidies and incentives provided by the U.S. Government and the state of New York as parts of the CHIPS for America act introduced last year. It should also be noted that Fab 8 in Malta recently recieved ITAR certification for DoD production on its 45 nm process, expanding GlobalFoundries' value as a home-grown chip manufacturer to the US government.

Back in 2020 GlobalFoundries earned approximately $5.7 billion in revenue, down from $6.176 billion in 2017. The company projects that in 2021 its revenue will grow by 9% to 10% year-over-year as a result of unprecedented demand. 

Since demand for chips is growing and governments have investments almost ready to go, it would seems to be a good time for GlobalFoundries' initial public offering. Previously GlobalFoundries planned to go public in late 2022 or early 2023, but the company appears to be thinking about bringing it forward into the late 2021 timeframe. Currently GlobalFoundries is wholly owned by Mubadala, an Emerati state-owned holding company.

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Report: Semi Demand 30% Above Supply, 20% Year-on-Year Growth

Semiconductor foundry offerings are thriving due to unprecedented demand for semiconductors and processors in recent quarters. Analysts from TrendForce believe that in Q1 2021 foundries will increase their revenue by 20% year-over-year as their capaci…

Semiconductor foundry offerings are thriving due to unprecedented demand for semiconductors and processors in recent quarters. Analysts from TrendForce believe that in Q1 2021 foundries will increase their revenue by 20% year-over-year as their capacities are fully loaded. Since the demand for chips is projected to continue to exceed the constrained supply for several quarters, market observers predict that manufacturers will be busy for a long time, and beyond this, will take a long time to catch up. This is good news for foundry revenue, and may encourage others to widen their foundry offerings. Warnings however about fab equipment are coming into play - being fully loaded means equipment now wears out faster, which increases risks of disruptions should that equipment also be short on supply.

TSMC Details 3nm Process Technology: Full Node Scaling for 2H22 Volume Production

At TSMC’s annual Technology Symposium, the Taiwanese semiconductor manufacturer detailed characteristics of its future 3nm process node as well as laying out a roadmap for 5nm successors in the form of N5P and N4 process nodes.

Starting off w…

At TSMC’s annual Technology Symposium, the Taiwanese semiconductor manufacturer detailed characteristics of its future 3nm process node as well as laying out a roadmap for 5nm successors in the form of N5P and N4 process nodes.

Starting off with TSMC’s upcoming N5 process node which represents its 2nd generation deep-ultraviolet (DUV) and extreme-ultraviolet (EUV) process node after the rarely used N7+ node (Used by the Kirin 990 SoC for example). TSMC has been in mass production for several months now as we’re expecting silicon shipping to customers at this moment with consumer products shipping this year – Apple’s next-generation SoCs being the likely first candidates for the node.

TSMC details that N5 currently is progressing with defect densities one quarter ahead of N7, with the new node having better yields at the time of mass production than both their predecessor major nodes N7 and N10, with a projected defect density that’s supposed to continue to improve past the historic trends of the last two generations.

The foundry is preparing a new N5P node that’s based on the current N5 process that extends its performance and power efficiency with a 5% speed gain and a 10% power reduction.

Beyond N5P, TSMC is also introducing the N4 node that represents a further evolution from the N5 process, employing further EUV layers to reduce masks, with minimal migration work required by chip designers. We’ll be seeing N4 risk production start in 4Q21 for volume production later in 2022.

Today’s biggest news was TSMC’s disclosure on their next big leap past the N5 process node generation family, which is the 3nm N3 node. We’ve heard that TSMC had been working on defining the node back last year with progress going well.

Contrary to Samsung’s 3nm process node which makes use of GAA (Gate-all-around) transistor structures, TSMC will instead be sticking with FinFET transistors and relying on “innovative features” to enable them to achieve the full-node scaling that N3 promises to bring.

Advertised PPA Improvements of New Process Technologies
Data announced during conference calls, events, press briefings and press releases
  TSMC
N7
vs
16FF+
N7
vs
N10
N7P
vs
N7
N7+
vs
N7
N5
vs
N7
N5P
vs
N5
N3
vs
N5
Power -60% <-40% -10% -15% -30% -10% -25-30%
Performance +30% ? +7% +10% +15% +5% +10-15%
Logic Area

Reduction %

(Density)


70%


>37%


-


~17%
0.55x

-45%

(1.8x)


-
0.58x

-42%

(1.7x)
Volume
Manufacturing

 

 

 
Q2 2019
 
Q2 2020 2021 H2 2022

Compared to it’s N5 node, N3 promises to improve performance by 10-15% at the same power levels, or reduce power by 25-30% at the same transistor speeds. Furthermore, TSMC promises a logic area density improvement of 1.7x, meaning that we’ll see a 0.58x scaling factor between N5 and N3 logic. This aggressive shrink doesn’t directly translate to all structures, as SRAM density is disclosed at only getting a 20% improvement which would mean a 0.8x scaling factor, and analog structures scaling even worse at 1.1x the density.

Modern chip designs are very SRAM-heavy with a rule-of-thumb ratio of 70/30 SRAM to logic ratio, so on a chip level the expected die shrink would only be ~26% or less.

N3 is planned to enter risk production in 2021 and enter volume production in 2H22. TSMC’s disclosed process characteristics on N3 would track closely with Samsung’s disclosures on 3GAE in terms of power and performance, but would lead more considerably in terms of density.

We’ll be posting more detailed content from TSMC’s Technology Symposium in due course, so please stay tuned for more information and updates.

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Marvell Unveils its Comprehensive Custom ASIC Offering

Last week Marvell had updated us with an overview of the company’s new more extensive and comprehensive custom ASIC offerings, detailing the company’s design abilities gained through the company’s acquisition of AveraSemi in 2019. For customers who are seeking to deploy differentiated products in the infrastructure and enterprise space without spinning up their own design teams, it seems like a no-brainer business proposition.

Last week Marvell had updated us with an overview of the company’s new more extensive and comprehensive custom ASIC offerings, detailing the company’s design abilities gained through the company's acquisition of AveraSemi in 2019. For customers who are seeking to deploy differentiated products in the infrastructure and enterprise space without spinning up their own design teams, it seems like a no-brainer business proposition.

Altair Semiconductor Renames to Sony Semiconductor Israel

Today, after more than four years of being acquired by Sony, Altair Semiconductor is renaming itself as Sony Semiconductor Israel. The IoT focused company over the last few years has been growing its success under the Sony conglomerate, and has deepen…

Today, after more than four years of being acquired by Sony, Altair Semiconductor is renaming itself as Sony Semiconductor Israel. The IoT focused company over the last few years has been growing its success under the Sony conglomerate, and has deepened its integration with Sony’s other semiconductor businesses.

We have been honored to be part of Sony for the past four years, playing a key role in the company’s core business,” says Sony Semiconductor Israel CEO Nohik Semel, “To better reflect our long-term commitment to our partners and customers, as well as the quality of our offering, we have decided to change Altair’s company name to Sony.”

As an example of the collaboration over the last few years, we’ve seen Sony employ AI DSP IP developed by Altair/Sony Semiconductor Israel that’s been deployed in the new IMX500/501 image sensor, integrating a AI inference block within the sensor’s logic die.

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